
Obj/FWlib_apt32f172_tc0_gpt.o:     file format elf32-csky-little


Disassembly of section .text:

00000000 <GPT_RESET_VALUE>:
//*GPTCHX:GPTCH0,GPTCH1,GPTCH2
//ReturnValue:NONE
/*************************************************************/  
void GPT_RESET_VALUE(CSP_GPT_T *GPTCHX)									//reset value
{
	GPTCHX->ECR		=	GPT_ECR_RST;          		/**< ECR reset value       */
   0:	3300      	movi      	r3, 0
   2:	b074      	st.w      	r3, (r0, 0x50)
	GPTCHX->DCR		=	GPT_DCR_RST;	     	 	/**< DCR reset value       */
   4:	b075      	st.w      	r3, (r0, 0x54)
	GPTCHX->PMSR	=	GPT_PMSR_RST;	     		/**< PMSR reset value      */
   6:	106f      	lrw      	r3, 0x2aaaaaa0	// 40 <GPT_RESET_VALUE+0x40>
   8:	b076      	st.w      	r3, (r0, 0x58)
	GPTCHX->CR		=	GPT_CR_RST;           		/**< CR reset value        */
   a:	3300      	movi      	r3, 0
   c:	b078      	st.w      	r3, (r0, 0x60)
	GPTCHX->MR		=	GPT_MR_RST;          		/**< MR reset value        */
   e:	b079      	st.w      	r3, (r0, 0x64)
	GPTCHX->CSR		= 	GPT_CSR_RST;         		/**< CSR reset value       */
  10:	b07b      	st.w      	r3, (r0, 0x6c)
	GPTCHX->SR 		=	GPT_SR_RST;           		/**< SR reset value        */
  12:	b07c      	st.w      	r3, (r0, 0x70)
	GPTCHX->IER		=	GPT_IER_RST;          		/**< IER reset value       */
  14:	b07d      	st.w      	r3, (r0, 0x74)
	GPTCHX->IDR		=	GPT_IDR_RST;          		/**< IDR reset value       */
  16:	b07e      	st.w      	r3, (r0, 0x78)
	GPTCHX->IMR		=	GPT_IMR_RST;          		/**< IMR Rreset value      */
  18:	b07f      	st.w      	r3, (r0, 0x7c)
	GPTCHX->CV		=	GPT_CV_RST;           		/**< CV reset value        */
  1a:	207f      	addi      	r0, 128
  1c:	b060      	st.w      	r3, (r0, 0)
	GPTCHX->RA		= 	GPT_RA_RST;           	 	/**< RA reset value        */
	GPTCHX->RB		=	GPT_RB_RST;           	 	/**< RB reset value        */
	GPTCHX->RC		=	GPT_RC_RST;           		/**< RC reset value        */
	
	GPT->BCR	=	GPT_BCR_RST;          			/**< BCR reset value       */
  1e:	32c0      	movi      	r2, 192
	GPTCHX->RA		= 	GPT_RA_RST;           	 	/**< RA reset value        */
  20:	b061      	st.w      	r3, (r0, 0x4)
	GPTCHX->RB		=	GPT_RB_RST;           	 	/**< RB reset value        */
  22:	b062      	st.w      	r3, (r0, 0x8)
	GPTCHX->RC		=	GPT_RC_RST;           		/**< RC reset value        */
  24:	b063      	st.w      	r3, (r0, 0xc)
	GPT->BCR	=	GPT_BCR_RST;          			/**< BCR reset value       */
  26:	4242      	lsli      	r2, r2, 2
  28:	1067      	lrw      	r3, 0	// 44 <GPT_RESET_VALUE+0x44>
  2a:	3100      	movi      	r1, 0
  2c:	9360      	ld.w      	r3, (r3, 0)
  2e:	608c      	addu      	r2, r3
  30:	b220      	st.w      	r1, (r2, 0)
	GPT->BMR	=	GPT_BMR_RST;          			/**< BMR reset value       */
  32:	32c1      	movi      	r2, 193
  34:	4242      	lsli      	r2, r2, 2
  36:	60c8      	addu      	r3, r2
  38:	3200      	movi      	r2, 0
  3a:	b340      	st.w      	r2, (r3, 0)
}
  3c:	783c      	rts
  3e:	0000      	bkpt
  40:	2aaaaaa0 	.long	0x2aaaaaa0
  44:	00000000 	.long	0x00000000

00000048 <GPT_IO_Init>:
//GPT_IO_IO2B(0->PA0.14(AF1) ; 1->PA1.5(AF2))
//ReturnValue:NONE
/*************************************************************/
void GPT_IO_Init(GPT_IO_MODE_TypeDef  GPT_IO_MODE_X , U8_T GPT_IO_G )
{
	if(GPT_IO_MODE_X==GPT_IO_CLK0)
  48:	3841      	cmpnei      	r0, 1
  4a:	0816      	bt      	0x76	// 76 <GPT_IO_Init+0x2e>
	{
		if(GPT_IO_G==0)
  4c:	3940      	cmpnei      	r1, 0
  4e:	0809      	bt      	0x60	// 60 <GPT_IO_Init+0x18>
		{
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFFF0F)|0x00000050;										//GPT_IO_CLK0(PA0.1->AF2)
  50:	1360      	lrw      	r3, 0	// 1d0 <GPT_IO_Init+0x188>
	}
	else if(GPT_IO_MODE_X==GPT_IO_ETR)
	{
		if(GPT_IO_G==0)
		{
			GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFF0F)|0x00000050;										//GPT_IO_ETR(PB0.1->AF2)
  52:	9340      	ld.w      	r2, (r3, 0)
  54:	9260      	ld.w      	r3, (r2, 0)
  56:	31f0      	movi      	r1, 240
  58:	68c5      	andn      	r3, r1
  5a:	3ba4      	bseti      	r3, r3, 4
  5c:	3ba6      	bseti      	r3, r3, 6
  5e:	040a      	br      	0x72	// 72 <GPT_IO_Init+0x2a>
		else if(GPT_IO_G==1)
  60:	3941      	cmpnei      	r1, 1
  62:	0809      	bt      	0x74	// 74 <GPT_IO_Init+0x2c>
			GPIOD0->CONLR=(GPIOD0->CONLR & 0XFFFFFF0F)|0x00000060;										//GPT_IO_CLK0(PD0.1->AF3)
  64:	127c      	lrw      	r3, 0	// 1d4 <GPT_IO_Init+0x18c>
  66:	9340      	ld.w      	r2, (r3, 0)
  68:	9260      	ld.w      	r3, (r2, 0)
  6a:	31f0      	movi      	r1, 240
  6c:	68c5      	andn      	r3, r1
  6e:	3ba5      	bseti      	r3, r3, 5
  70:	3ba6      	bseti      	r3, r3, 6
  72:	b260      	st.w      	r3, (r2, 0)
		else if(GPT_IO_G==1)
		{
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFF0FFFFF)|0x00500000;										//GPT_IO_IO1A(PA1.5->AF2)
		}
	}
}
  74:	783c      	rts
	else if(GPT_IO_MODE_X==GPT_IO_CLK1)
  76:	3842      	cmpnei      	r0, 2
  78:	080c      	bt      	0x90	// 90 <GPT_IO_Init+0x48>
		if(GPT_IO_G==0)
  7a:	3940      	cmpnei      	r1, 0
  7c:	0bfc      	bt      	0x74	// 74 <GPT_IO_Init+0x2c>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0X0FFFFFFF)|0x60000000;										//GPT_IO_CLK1(PA0.15->AF3)
  7e:	1275      	lrw      	r3, 0	// 1d0 <GPT_IO_Init+0x188>
  80:	9340      	ld.w      	r2, (r3, 0)
  82:	9261      	ld.w      	r3, (r2, 0x4)
  84:	4364      	lsli      	r3, r3, 4
  86:	4b64      	lsri      	r3, r3, 4
  88:	3bbd      	bseti      	r3, r3, 29
  8a:	3bbe      	bseti      	r3, r3, 30
  8c:	b261      	st.w      	r3, (r2, 0x4)
  8e:	07f3      	br      	0x74	// 74 <GPT_IO_Init+0x2c>
	else if(GPT_IO_MODE_X==GPT_IO_CLK2)
  90:	3843      	cmpnei      	r0, 3
  92:	0805      	bt      	0x9c	// 9c <GPT_IO_Init+0x54>
		if(GPT_IO_G==0)
  94:	3940      	cmpnei      	r1, 0
  96:	0bef      	bt      	0x74	// 74 <GPT_IO_Init+0x2c>
			GPIOC0->CONLR=(GPIOC0->CONLR & 0XFFFFFF0F)|0x00000060;										//GPT_IO_CLK2(PC0.1->AF3)
  98:	1270      	lrw      	r3, 0	// 1d8 <GPT_IO_Init+0x190>
  9a:	07e6      	br      	0x66	// 66 <GPT_IO_Init+0x1e>
	else if(GPT_IO_MODE_X==GPT_IO_ETR)
  9c:	3844      	cmpnei      	r0, 4
  9e:	080f      	bt      	0xbc	// bc <GPT_IO_Init+0x74>
		if(GPT_IO_G==0)
  a0:	3940      	cmpnei      	r1, 0
  a2:	0803      	bt      	0xa8	// a8 <GPT_IO_Init+0x60>
			GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFF0F)|0x00000050;										//GPT_IO_ETR(PB0.1->AF2)
  a4:	126e      	lrw      	r3, 0	// 1dc <GPT_IO_Init+0x194>
  a6:	07d6      	br      	0x52	// 52 <GPT_IO_Init+0xa>
		else if(GPT_IO_G==1)
  a8:	3941      	cmpnei      	r1, 1
  aa:	0be5      	bt      	0x74	// 74 <GPT_IO_Init+0x2c>
			GPIOC0->CONLR=(GPIOC0->CONLR & 0XFFFFFFF0)|0x00000006;										//GPT_IO_ETR(PC0.0->AF3)
  ac:	126b      	lrw      	r3, 0	// 1d8 <GPT_IO_Init+0x190>
  ae:	310f      	movi      	r1, 15
  b0:	9340      	ld.w      	r2, (r3, 0)
  b2:	9260      	ld.w      	r3, (r2, 0)
  b4:	68c5      	andn      	r3, r1
  b6:	3ba1      	bseti      	r3, r3, 1
  b8:	3ba2      	bseti      	r3, r3, 2
  ba:	07dc      	br      	0x72	// 72 <GPT_IO_Init+0x2a>
	else if(GPT_IO_MODE_X==GPT_IO_IO0A)
  bc:	3845      	cmpnei      	r0, 5
  be:	0825      	bt      	0x108	// 108 <GPT_IO_Init+0xc0>
		if(GPT_IO_G==0)
  c0:	3940      	cmpnei      	r1, 0
  c2:	0803      	bt      	0xc8	// c8 <GPT_IO_Init+0x80>
			GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFF0F)|0x00000060;										//GPT_IO_IO0A(PB0.1->AF3)
  c4:	1266      	lrw      	r3, 0	// 1dc <GPT_IO_Init+0x194>
  c6:	07d0      	br      	0x66	// 66 <GPT_IO_Init+0x1e>
		else if(GPT_IO_G==1)
  c8:	3941      	cmpnei      	r1, 1
  ca:	080c      	bt      	0xe2	// e2 <GPT_IO_Init+0x9a>
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFF0FFF)|0x00007000;										//GPT_IO_IO0A(PA0.3->AF4)
  cc:	1261      	lrw      	r3, 0	// 1d0 <GPT_IO_Init+0x188>
  ce:	32f0      	movi      	r2, 240
  d0:	9320      	ld.w      	r1, (r3, 0)
  d2:	4248      	lsli      	r2, r2, 8
  d4:	9160      	ld.w      	r3, (r1, 0)
  d6:	68c9      	andn      	r3, r2
  d8:	32e0      	movi      	r2, 224
  da:	4247      	lsli      	r2, r2, 7
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFF0FFFF)|0x00070000;										//GPT_IO_IO0B(PA0.4->AF4)
  dc:	6cc8      	or      	r3, r2
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFF0FFFFF)|0x00500000;										//GPT_IO_IO1A(PA1.5->AF2)
  de:	b160      	st.w      	r3, (r1, 0)
}
  e0:	07ca      	br      	0x74	// 74 <GPT_IO_Init+0x2c>
		else if(GPT_IO_G==2)
  e2:	3942      	cmpnei      	r1, 2
  e4:	0808      	bt      	0xf4	// f4 <GPT_IO_Init+0xac>
			GPIOD0->CONLR=(GPIOD0->CONLR & 0XFFFFFFF0)|0x00000004;										//GPT_IO_IO0A(PD0.0->AF1)
  e6:	117c      	lrw      	r3, 0	// 1d4 <GPT_IO_Init+0x18c>
  e8:	310f      	movi      	r1, 15
  ea:	9340      	ld.w      	r2, (r3, 0)
  ec:	9260      	ld.w      	r3, (r2, 0)
  ee:	68c5      	andn      	r3, r1
  f0:	3ba2      	bseti      	r3, r3, 2
  f2:	07c0      	br      	0x72	// 72 <GPT_IO_Init+0x2a>
		else if(GPT_IO_G==3)
  f4:	3943      	cmpnei      	r1, 3
  f6:	0bbf      	bt      	0x74	// 74 <GPT_IO_Init+0x2c>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFFFFF0)|0x00000005;										//GPT_IO_IO0A(PA1.0->AF2)
  f8:	117a      	lrw      	r3, 0	// 1e0 <GPT_IO_Init+0x198>
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFFFF0)|0x00000006;										//GPT_IO_IO0B(PA0.0->AF3)
  fa:	9340      	ld.w      	r2, (r3, 0)
  fc:	9260      	ld.w      	r3, (r2, 0)
  fe:	310f      	movi      	r1, 15
 100:	68c5      	andn      	r3, r1
 102:	6c0c      	or      	r0, r3
 104:	b200      	st.w      	r0, (r2, 0)
 106:	07b7      	br      	0x74	// 74 <GPT_IO_Init+0x2c>
	else if(GPT_IO_MODE_X==GPT_IO_IO0B)
 108:	3846      	cmpnei      	r0, 6
 10a:	081d      	bt      	0x144	// 144 <GPT_IO_Init+0xfc>
		if(GPT_IO_G==0)
 10c:	3940      	cmpnei      	r1, 0
 10e:	0803      	bt      	0x114	// 114 <GPT_IO_Init+0xcc>
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFFFF0)|0x00000006;										//GPT_IO_IO0B(PA0.0->AF3)
 110:	1170      	lrw      	r3, 0	// 1d0 <GPT_IO_Init+0x188>
 112:	07f4      	br      	0xfa	// fa <GPT_IO_Init+0xb2>
		else if(GPT_IO_G==1)
 114:	3941      	cmpnei      	r1, 1
 116:	080a      	bt      	0x12a	// 12a <GPT_IO_Init+0xe2>
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFF0FFFF)|0x00070000;										//GPT_IO_IO0B(PA0.4->AF4)
 118:	116e      	lrw      	r3, 0	// 1d0 <GPT_IO_Init+0x188>
 11a:	32f0      	movi      	r2, 240
 11c:	9320      	ld.w      	r1, (r3, 0)
 11e:	424c      	lsli      	r2, r2, 12
 120:	9160      	ld.w      	r3, (r1, 0)
 122:	68c9      	andn      	r3, r2
 124:	32e0      	movi      	r2, 224
 126:	424b      	lsli      	r2, r2, 11
 128:	07da      	br      	0xdc	// dc <GPT_IO_Init+0x94>
		else if(GPT_IO_G==2)
 12a:	3942      	cmpnei      	r1, 2
 12c:	0808      	bt      	0x13c	// 13c <GPT_IO_Init+0xf4>
			GPIOD0->CONLR=(GPIOD0->CONLR & 0XFFFFFF0F)|0x00000040;										//GPT_IO_IO0B(PD0.1->AF1)
 12e:	116a      	lrw      	r3, 0	// 1d4 <GPT_IO_Init+0x18c>
 130:	31f0      	movi      	r1, 240
 132:	9340      	ld.w      	r2, (r3, 0)
 134:	9260      	ld.w      	r3, (r2, 0)
 136:	68c5      	andn      	r3, r1
 138:	3ba6      	bseti      	r3, r3, 6
 13a:	079c      	br      	0x72	// 72 <GPT_IO_Init+0x2a>
		else if(GPT_IO_G==3)
 13c:	3943      	cmpnei      	r1, 3
 13e:	0b9b      	bt      	0x74	// 74 <GPT_IO_Init+0x2c>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFFFF0F)|0x00000050;										//GPT_IO_IO0B(PA1.1->AF2)
 140:	1168      	lrw      	r3, 0	// 1e0 <GPT_IO_Init+0x198>
 142:	0788      	br      	0x52	// 52 <GPT_IO_Init+0xa>
	else if(GPT_IO_MODE_X==GPT_IO_IO1A)
 144:	3847      	cmpnei      	r0, 7
 146:	0817      	bt      	0x174	// 174 <GPT_IO_Init+0x12c>
		if(GPT_IO_G==0)
 148:	3940      	cmpnei      	r1, 0
 14a:	080a      	bt      	0x15e	// 15e <GPT_IO_Init+0x116>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFF0FFF)|0x00004000;										//GPT_IO_IO1A(PA0.11->AF1)
 14c:	1161      	lrw      	r3, 0	// 1d0 <GPT_IO_Init+0x188>
 14e:	32f0      	movi      	r2, 240
 150:	9320      	ld.w      	r1, (r3, 0)
 152:	9161      	ld.w      	r3, (r1, 0x4)
 154:	4248      	lsli      	r2, r2, 8
 156:	68c9      	andn      	r3, r2
 158:	3bae      	bseti      	r3, r3, 14
			GPIOA0->CONHR=(GPIOA0->CONHR & 0XF0FFFFFF)|0x04000000;										//GPT_IO_IO2B(PA0.14->AF1)
 15a:	b161      	st.w      	r3, (r1, 0x4)
 15c:	078c      	br      	0x74	// 74 <GPT_IO_Init+0x2c>
		else if(GPT_IO_G==1)
 15e:	3941      	cmpnei      	r1, 1
 160:	0b8a      	bt      	0x74	// 74 <GPT_IO_Init+0x2c>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFFF0FF)|0x00000500;										//GPT_IO_IO1A(PA1.2->AF2)
 162:	1160      	lrw      	r3, 0	// 1e0 <GPT_IO_Init+0x198>
 164:	32f0      	movi      	r2, 240
 166:	9320      	ld.w      	r1, (r3, 0)
 168:	9160      	ld.w      	r3, (r1, 0)
 16a:	4244      	lsli      	r2, r2, 4
 16c:	68c9      	andn      	r3, r2
 16e:	3ba8      	bseti      	r3, r3, 8
 170:	3baa      	bseti      	r3, r3, 10
 172:	07b6      	br      	0xde	// de <GPT_IO_Init+0x96>
	else if(GPT_IO_MODE_X==GPT_IO_IO1B)
 174:	3848      	cmpnei      	r0, 8
 176:	0816      	bt      	0x1a2	// 1a2 <GPT_IO_Init+0x15a>
		if(GPT_IO_G==0)
 178:	3940      	cmpnei      	r1, 0
 17a:	0809      	bt      	0x18c	// 18c <GPT_IO_Init+0x144>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFF0FFFF)|0x00040000;										//GPT_IO_IO1A(PA0.12->AF1)
 17c:	1075      	lrw      	r3, 0	// 1d0 <GPT_IO_Init+0x188>
 17e:	32f0      	movi      	r2, 240
 180:	9320      	ld.w      	r1, (r3, 0)
 182:	9161      	ld.w      	r3, (r1, 0x4)
 184:	424c      	lsli      	r2, r2, 12
 186:	68c9      	andn      	r3, r2
 188:	3bb2      	bseti      	r3, r3, 18
 18a:	07e8      	br      	0x15a	// 15a <GPT_IO_Init+0x112>
		else if(GPT_IO_G==1)
 18c:	3941      	cmpnei      	r1, 1
 18e:	0b73      	bt      	0x74	// 74 <GPT_IO_Init+0x2c>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFF0FFF)|0x00005000;										//GPT_IO_IO1A(PA1.3->AF2)
 190:	1074      	lrw      	r3, 0	// 1e0 <GPT_IO_Init+0x198>
 192:	32f0      	movi      	r2, 240
 194:	9320      	ld.w      	r1, (r3, 0)
 196:	9160      	ld.w      	r3, (r1, 0)
 198:	4248      	lsli      	r2, r2, 8
 19a:	68c9      	andn      	r3, r2
 19c:	3bac      	bseti      	r3, r3, 12
 19e:	3bae      	bseti      	r3, r3, 14
 1a0:	079f      	br      	0xde	// de <GPT_IO_Init+0x96>
	else if(GPT_IO_MODE_X==GPT_IO_IO2A)
 1a2:	3849      	cmpnei      	r0, 9
 1a4:	0820      	bt      	0x1e4	// 1e4 <GPT_IO_Init+0x19c>
		if(GPT_IO_G==0)
 1a6:	3940      	cmpnei      	r1, 0
 1a8:	0809      	bt      	0x1ba	// 1ba <GPT_IO_Init+0x172>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0XFF0FFFFF)|0x00400000;										//GPT_IO_IO2A(PA0.13->AF1)
 1aa:	106a      	lrw      	r3, 0	// 1d0 <GPT_IO_Init+0x188>
 1ac:	32f0      	movi      	r2, 240
 1ae:	9320      	ld.w      	r1, (r3, 0)
 1b0:	9161      	ld.w      	r3, (r1, 0x4)
 1b2:	4250      	lsli      	r2, r2, 16
 1b4:	68c9      	andn      	r3, r2
 1b6:	3bb6      	bseti      	r3, r3, 22
 1b8:	07d1      	br      	0x15a	// 15a <GPT_IO_Init+0x112>
		else if(GPT_IO_G==1)
 1ba:	3941      	cmpnei      	r1, 1
 1bc:	0b5c      	bt      	0x74	// 74 <GPT_IO_Init+0x2c>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFF0FFFF)|0x00050000;										//GPT_IO_IO2A(PA1.4->AF2)
 1be:	1069      	lrw      	r3, 0	// 1e0 <GPT_IO_Init+0x198>
 1c0:	32f0      	movi      	r2, 240
 1c2:	9320      	ld.w      	r1, (r3, 0)
 1c4:	9160      	ld.w      	r3, (r1, 0)
 1c6:	424c      	lsli      	r2, r2, 12
 1c8:	68c9      	andn      	r3, r2
 1ca:	3bb0      	bseti      	r3, r3, 16
 1cc:	3bb2      	bseti      	r3, r3, 18
 1ce:	0788      	br      	0xde	// de <GPT_IO_Init+0x96>
	...
	else if(GPT_IO_MODE_X==GPT_IO_IO2B)
 1e4:	384a      	cmpnei      	r0, 10
 1e6:	0b47      	bt      	0x74	// 74 <GPT_IO_Init+0x2c>
		if(GPT_IO_G==0)
 1e8:	3940      	cmpnei      	r1, 0
 1ea:	0809      	bt      	0x1fc	// 1fc <GPT_IO_Init+0x1b4>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0XF0FFFFFF)|0x04000000;										//GPT_IO_IO2B(PA0.14->AF1)
 1ec:	1365      	lrw      	r3, 0	// 380 <GPTCHX_PWM_Configure+0x66>
 1ee:	32f0      	movi      	r2, 240
 1f0:	9320      	ld.w      	r1, (r3, 0)
 1f2:	9161      	ld.w      	r3, (r1, 0x4)
 1f4:	4254      	lsli      	r2, r2, 20
 1f6:	68c9      	andn      	r3, r2
 1f8:	3bba      	bseti      	r3, r3, 26
 1fa:	07b0      	br      	0x15a	// 15a <GPT_IO_Init+0x112>
		else if(GPT_IO_G==1)
 1fc:	3941      	cmpnei      	r1, 1
 1fe:	0b3b      	bt      	0x74	// 74 <GPT_IO_Init+0x2c>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFF0FFFFF)|0x00500000;										//GPT_IO_IO1A(PA1.5->AF2)
 200:	1361      	lrw      	r3, 0	// 384 <GPTCHX_PWM_Configure+0x6a>
 202:	32f0      	movi      	r2, 240
 204:	9320      	ld.w      	r1, (r3, 0)
 206:	9160      	ld.w      	r3, (r1, 0)
 208:	4250      	lsli      	r2, r2, 16
 20a:	68c9      	andn      	r3, r2
 20c:	3bb4      	bseti      	r3, r3, 20
 20e:	3bb6      	bseti      	r3, r3, 22
 210:	0767      	br      	0xde	// de <GPT_IO_Init+0x96>

00000212 <All_GPT_SoftwareReset>:
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/ 
void All_GPT_SoftwareReset(void)
{
	GPT->BCR = 0x01;							// all GPT Software reset
 212:	127e      	lrw      	r3, 0	// 388 <GPTCHX_PWM_Configure+0x6e>
 214:	32c0      	movi      	r2, 192
 216:	9360      	ld.w      	r3, (r3, 0)
 218:	4242      	lsli      	r2, r2, 2
 21a:	60c8      	addu      	r3, r2
 21c:	3201      	movi      	r2, 1
 21e:	b340      	st.w      	r2, (r3, 0)
}
 220:	783c      	rts

00000222 <All_GPT_SWTRG>:
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/ 
void All_GPT_SWTRG(void)
{
	GPT->BCR = 0x02;							// all GPT SWTRG
 222:	127a      	lrw      	r3, 0	// 388 <GPTCHX_PWM_Configure+0x6e>
 224:	32c0      	movi      	r2, 192
 226:	9360      	ld.w      	r3, (r3, 0)
 228:	4242      	lsli      	r2, r2, 2
 22a:	60c8      	addu      	r3, r2
 22c:	3202      	movi      	r2, 2
 22e:	b340      	st.w      	r2, (r3, 0)
}
 230:	783c      	rts

00000232 <GPTCHX_SWTRG>:
//*GPTCHX:GPTCH0,GPTCH1,GPTCH2
//ReturnValue:NONE
/*************************************************************/ 
void GPTCHX_SWTRG(CSP_GPT_T *GPTCHX)
{
	GPTCHX->CR = 0x08;							//GPTCHX SWTRG
 232:	3308      	movi      	r3, 8
 234:	b078      	st.w      	r3, (r0, 0x60)
}
 236:	783c      	rts

00000238 <GPTCHX_SoftwareReset>:
//*GPTCHX:GPTCH0,GPTCH1,GPTCH2
//ReturnValue:NONE
/*************************************************************/ 
void GPTCHX_SoftwareReset(CSP_GPT_T *GPTCHX)
{
	GPTCHX->CR = 0x01;							//GPTCHX Software reset
 238:	3301      	movi      	r3, 1
 23a:	b078      	st.w      	r3, (r0, 0x60)
}
 23c:	783c      	rts

0000023e <GPTCHX_CountClk_CMD>:
//NewState:DISABLE,ENABLE
//ReturnValue:NONE
/*************************************************************/ 
void GPTCHX_CountClk_CMD(CSP_GPT_T *GPTCHX , FunctionalStatus NewState)
{
	if(NewState != DISABLE)
 23e:	3940      	cmpnei      	r1, 0
 240:	0c04      	bf      	0x248	// 248 <GPTCHX_CountClk_CMD+0xa>
	{
		GPTCHX->CR = 0x02;							//enable counter clk 
 242:	3302      	movi      	r3, 2
	}
	else
	{
		GPTCHX->CR = 0x04;							//Disable counter clk 
 244:	b078      	st.w      	r3, (r0, 0x60)
	}
}
 246:	783c      	rts
		GPTCHX->CR = 0x04;							//Disable counter clk 
 248:	3304      	movi      	r3, 4
 24a:	07fd      	br      	0x244	// 244 <GPTCHX_CountClk_CMD+0x6>

0000024c <GPTCHX_Clk_CMD>:
//NewState:DISABLE,ENABLE
//ReturnValue:NONE
/*************************************************************/
void GPTCHX_Clk_CMD(CSP_GPT_T *GPTCHX , FunctionalStatus NewState)
{
	if(NewState != DISABLE)
 24c:	3940      	cmpnei      	r1, 0
	{
		GPTCHX->ECR	=0X02;									//GPT CLK enable
 24e:	3302      	movi      	r3, 2
	if(NewState != DISABLE)
 250:	0c08      	bf      	0x260	// 260 <GPTCHX_Clk_CMD+0x14>
		GPTCHX->ECR	=0X02;									//GPT CLK enable
 252:	b074      	st.w      	r3, (r0, 0x50)
		while(!(GPTCHX->PMSR&0X02));
 254:	3202      	movi      	r2, 2
 256:	9076      	ld.w      	r3, (r0, 0x58)
 258:	68c8      	and      	r3, r2
 25a:	3b40      	cmpnei      	r3, 0
 25c:	0ffd      	bf      	0x256	// 256 <GPTCHX_Clk_CMD+0xa>
	else 
	{
		GPTCHX->DCR	=0X02;									//GPT CLK disable
		while(GPTCHX->PMSR&0X02);
	}
}
 25e:	783c      	rts
		GPTCHX->DCR	=0X02;									//GPT CLK disable
 260:	b075      	st.w      	r3, (r0, 0x54)
		while(GPTCHX->PMSR&0X02);
 262:	3202      	movi      	r2, 2
 264:	9076      	ld.w      	r3, (r0, 0x58)
 266:	68c8      	and      	r3, r2
 268:	3b40      	cmpnei      	r3, 0
 26a:	0bfd      	bt      	0x264	// 264 <GPTCHX_Clk_CMD+0x18>
 26c:	07f9      	br      	0x25e	// 25e <GPTCHX_Clk_CMD+0x12>

0000026e <GPTCHX_Set_RA_RB_RC>:
//load_RC:0~0xffff
//ReturnValue:NONE
/*************************************************************/ 
void GPTCHX_Set_RA_RB_RC(CSP_GPT_T *GPTCHX , U16_T load_RA , U16_T load_RB , U16_T load_RC)
{
	GPTCHX->RA = load_RA;											//Set GPT RA
 26e:	207f      	addi      	r0, 128
 270:	b021      	st.w      	r1, (r0, 0x4)
	GPTCHX->RB = load_RB;											//Set GPT RB
 272:	b042      	st.w      	r2, (r0, 0x8)
	GPTCHX->RC = load_RC;											//Set GPT RC
 274:	b063      	st.w      	r3, (r0, 0xc)
}
 276:	783c      	rts

00000278 <GPTCHX_CLK_Configure>:
//GPTCHX_BURST_SET_X:GPTCHX_BURST_SET_None,GPTCHX_BURST_SET_XC0,GPTCHX_BURST_SET_XC1,GPTCHX_BURST_SET_XC2
//ReturnValue:NONE
/*************************************************************/
void GPTCHX_CLK_Configure(CSP_GPT_T *GPTCHX , GPT_Mclk_Selecte_TypeDef GPT_Mclk_Selecte_X , GptClks_Selecte_TypeDef GptClks_Selecte_X ,
						GPTCHX_CLKI_SET_TypeDef GPTCHX_CLKI_X , GPTCHX_BURST_SET_TypeDef GPTCHX_BURST_SET_X)
{
 278:	14c3      	push      	r4-r6
 27a:	9883      	ld.w      	r4, (sp, 0xc)
 27c:	6d93      	mov      	r6, r4
	GPTCHX->MR=GPTCHX->MR&0XFFFFFFC0;
 27e:	353f      	movi      	r5, 63
 280:	9099      	ld.w      	r4, (r0, 0x64)
 282:	6915      	andn      	r4, r5
 284:	b099      	st.w      	r4, (r0, 0x64)
	GPTCHX->MR|=GptClks_Selecte_X|GPTCHX_CLKI_X|GPTCHX_BURST_SET_X;
 286:	6cd8      	or      	r3, r6
 288:	9099      	ld.w      	r4, (r0, 0x64)
 28a:	6c8c      	or      	r2, r3
 28c:	6c90      	or      	r2, r4
 28e:	b059      	st.w      	r2, (r0, 0x64)
	GPT->BMR=GPT->BMR&0xFFFFFEFF;
 290:	32c1      	movi      	r2, 193
 292:	117e      	lrw      	r3, 0	// 388 <GPTCHX_PWM_Configure+0x6e>
 294:	4242      	lsli      	r2, r2, 2
 296:	9360      	ld.w      	r3, (r3, 0)
 298:	60c8      	addu      	r3, r2
 29a:	9340      	ld.w      	r2, (r3, 0)
 29c:	3a88      	bclri      	r2, r2, 8
 29e:	b340      	st.w      	r2, (r3, 0)
	GPT->BMR|=GPT_Mclk_Selecte_X;								//MCLK选择PCLK或者96MHz		
 2a0:	9340      	ld.w      	r2, (r3, 0)
 2a2:	6c84      	or      	r2, r1
 2a4:	b340      	st.w      	r2, (r3, 0)
	if(GPT_Mclk_Selecte_X==GPT_Mclk_Selecte_HFOSC)				//若选择96MHz需要增加配置
 2a6:	3380      	movi      	r3, 128
 2a8:	4361      	lsli      	r3, r3, 1
 2aa:	64c6      	cmpne      	r1, r3
	GPTCHX->MR|=GptClks_Selecte_X|GPTCHX_CLKI_X|GPTCHX_BURST_SET_X;
 2ac:	6d5b      	mov      	r5, r6
	if(GPT_Mclk_Selecte_X==GPT_Mclk_Selecte_HFOSC)				//若选择96MHz需要增加配置
 2ae:	080c      	bt      	0x2c6	// 2c6 <GPTCHX_CLK_Configure+0x4e>
	{
		SYSCON->CLCR|=(0X01<<20);
 2b0:	1177      	lrw      	r3, 0	// 38c <GPTCHX_PWM_Configure+0x72>
		while(!(SYSCON->CLCR&(0x01<<21)));
 2b2:	3280      	movi      	r2, 128
		SYSCON->CLCR|=(0X01<<20);
 2b4:	9320      	ld.w      	r1, (r3, 0)
 2b6:	9174      	ld.w      	r3, (r1, 0x50)
 2b8:	3bb4      	bseti      	r3, r3, 20
 2ba:	b174      	st.w      	r3, (r1, 0x50)
		while(!(SYSCON->CLCR&(0x01<<21)));
 2bc:	424e      	lsli      	r2, r2, 14
 2be:	9174      	ld.w      	r3, (r1, 0x50)
 2c0:	68c8      	and      	r3, r2
 2c2:	3b40      	cmpnei      	r3, 0
 2c4:	0ffd      	bf      	0x2be	// 2be <GPTCHX_CLK_Configure+0x46>
	}
}
 2c6:	1483      	pop      	r4-r6

000002c8 <GPTCHX_XCn_Configure>:
//				XC2_Selecte_TCLK2,XC2_Selecte_TIOA0,XC2_Selecte_TIOA1,
//ReturnValue:NONE
/*************************************************************/ 
void GPTCHX_XCn_Configure(XCn_Configure_TypeDef XCn_Configure , XCn_Selecte_TypeDef XCn_Selecte_x)
{
	if(XCn_Configure==XC0_Configure)
 2c8:	3840      	cmpnei      	r0, 0
 2ca:	080e      	bt      	0x2e6	// 2e6 <GPTCHX_XCn_Configure+0x1e>
	{
		GPT->BMR=GPT->BMR&0xFFFFFFFC;
 2cc:	116f      	lrw      	r3, 0	// 388 <GPTCHX_PWM_Configure+0x6e>
 2ce:	32c1      	movi      	r2, 193
 2d0:	4242      	lsli      	r2, r2, 2
 2d2:	9360      	ld.w      	r3, (r3, 0)
 2d4:	60c8      	addu      	r3, r2
 2d6:	9340      	ld.w      	r2, (r3, 0)
 2d8:	3a80      	bclri      	r2, r2, 0
 2da:	3a81      	bclri      	r2, r2, 1
		GPT->BMR=GPT->BMR&0xFFFFFFF3;
		GPT->BMR|=XCn_Selecte_x;
	}
	else if(XCn_Configure==XC2_Configure)
	{
		GPT->BMR=GPT->BMR&0xFFFFFFCF;
 2dc:	b340      	st.w      	r2, (r3, 0)
		GPT->BMR|=XCn_Selecte_x;
 2de:	9340      	ld.w      	r2, (r3, 0)
 2e0:	6c48      	or      	r1, r2
 2e2:	b320      	st.w      	r1, (r3, 0)
	}
}
 2e4:	783c      	rts
	else if(XCn_Configure==XC1_Configure)
 2e6:	3842      	cmpnei      	r0, 2
 2e8:	080a      	bt      	0x2fc	// 2fc <GPTCHX_XCn_Configure+0x34>
		GPT->BMR=GPT->BMR&0xFFFFFFF3;
 2ea:	1168      	lrw      	r3, 0	// 388 <GPTCHX_PWM_Configure+0x6e>
 2ec:	32c1      	movi      	r2, 193
 2ee:	4242      	lsli      	r2, r2, 2
 2f0:	9360      	ld.w      	r3, (r3, 0)
 2f2:	60c8      	addu      	r3, r2
 2f4:	9340      	ld.w      	r2, (r3, 0)
 2f6:	3a82      	bclri      	r2, r2, 2
 2f8:	3a83      	bclri      	r2, r2, 3
 2fa:	07f1      	br      	0x2dc	// 2dc <GPTCHX_XCn_Configure+0x14>
	else if(XCn_Configure==XC2_Configure)
 2fc:	3843      	cmpnei      	r0, 3
 2fe:	0bf3      	bt      	0x2e4	// 2e4 <GPTCHX_XCn_Configure+0x1c>
		GPT->BMR=GPT->BMR&0xFFFFFFCF;
 300:	1162      	lrw      	r3, 0	// 388 <GPTCHX_PWM_Configure+0x6e>
 302:	32c1      	movi      	r2, 193
 304:	4242      	lsli      	r2, r2, 2
 306:	9360      	ld.w      	r3, (r3, 0)
 308:	60c8      	addu      	r3, r2
 30a:	9340      	ld.w      	r2, (r3, 0)
 30c:	3a84      	bclri      	r2, r2, 4
 30e:	3a85      	bclri      	r2, r2, 5
 310:	07e6      	br      	0x2dc	// 2dc <GPTCHX_XCn_Configure+0x14>

00000312 <GPTCHX_COUNT_Configure>:
//CPC_Reload_CMD:CPC_Reload_DISABLE,CPC_Reload_ENABLE
//ReturnValue:NONE
/*************************************************************/ 
void GPTCHX_COUNT_Configure(CSP_GPT_T *GPTCHX , CPC_TRG_CMD_TypeDef CPC_Reload_CMD)
{
	GPTCHX->MR|=CPC_Reload_CMD;
 312:	9079      	ld.w      	r3, (r0, 0x64)
 314:	6c4c      	or      	r1, r3
 316:	b039      	st.w      	r1, (r0, 0x64)
}
 318:	783c      	rts

0000031a <GPTCHX_PWM_Configure>:
//ReturnValue:NONE
/*************************************************************/ 
void GPTCHX_PWM_Configure(CSP_GPT_T *GPTCHX , CPC_STOP_CMD_TypeDef CPC_STOP_CMD , CPC_DisCountClk_CMD_TypeDef CPC_DisCountClk_CMD , CPC_TRG_CMD_TypeDef CPC_Reload_CMD , ENETRG_CMD_TypeDef EEVT_Reload_CMD , EEVT_SET_TypeDef EEVT_SET_X ,
						 TIOA_SWTRG_OutPutX_TypeDef TIOA_SWTRG_OutPutX , TIOA_EEVT_OutPutX_TypeDef TIOA_EEVT_OutPutX , TIOA_CPA_OutPutX_TypeDef TIOA_CPA_OutPutX , TIOA_CPC_OutPutX_TypeDef TIOA_CPC_OutPutX ,
						 TIOB_SWTRG_OutPutX_TypeDef TIOB_SWTRG_OutPutX , TIOB_EEVT_OutPutX_TypeDef TIOB_EEVT_OutPutX , TIOB_CPB_OutPutX_TypeDef TIOB_CPB_OutPutX , TIOB_CPC_OutPutX_TypeDef TIOB_CPC_OutPutX)
{
 31a:	14c4      	push      	r4-r7
 31c:	1428      	subi      	sp, sp, 32
 31e:	98ae      	ld.w      	r5, (sp, 0x38)
 320:	b8a1      	st.w      	r5, (sp, 0x4)
 322:	98af      	ld.w      	r5, (sp, 0x3c)
 324:	b8a2      	st.w      	r5, (sp, 0x8)
 326:	98b0      	ld.w      	r5, (sp, 0x40)
 328:	b8a3      	st.w      	r5, (sp, 0xc)
 32a:	98b1      	ld.w      	r5, (sp, 0x44)
 32c:	b8a4      	st.w      	r5, (sp, 0x10)
 32e:	98b2      	ld.w      	r5, (sp, 0x48)
 330:	b8a5      	st.w      	r5, (sp, 0x14)
 332:	98b3      	ld.w      	r5, (sp, 0x4c)
 334:	b8a6      	st.w      	r5, (sp, 0x18)
 336:	98b4      	ld.w      	r5, (sp, 0x50)
 338:	6dd7      	mov      	r7, r5
 33a:	98b5      	ld.w      	r5, (sp, 0x54)
 33c:	b8a7      	st.w      	r5, (sp, 0x1c)
	GPTCHX->MR=GPTCHX->MR&0X0000003F;
 33e:	363f      	movi      	r6, 63
 340:	90b9      	ld.w      	r5, (r0, 0x64)
 342:	6958      	and      	r5, r6
	GPTCHX->MR|=(0X01<<15)|CPC_STOP_CMD|CPC_DisCountClk_CMD|CPC_Reload_CMD|TIOA_SWTRG_OutPutX|TIOA_EEVT_OutPutX|TIOA_CPA_OutPutX|TIOA_CPC_OutPutX
 344:	98c7      	ld.w      	r6, (sp, 0x1c)
 346:	3eaf      	bseti      	r6, r6, 15
 348:	6d9c      	or      	r6, r7
 34a:	98e6      	ld.w      	r7, (sp, 0x18)
 34c:	6d9c      	or      	r6, r7
 34e:	98e4      	ld.w      	r7, (sp, 0x10)
 350:	6d9c      	or      	r6, r7
 352:	98e5      	ld.w      	r7, (sp, 0x14)
 354:	6d9c      	or      	r6, r7
 356:	98e3      	ld.w      	r7, (sp, 0xc)
 358:	6d9c      	or      	r6, r7
 35a:	98e2      	ld.w      	r7, (sp, 0x8)
 35c:	6d9c      	or      	r6, r7
 35e:	98e1      	ld.w      	r7, (sp, 0x4)
 360:	6d9c      	or      	r6, r7
 362:	6cd8      	or      	r3, r6
	GPTCHX->MR=GPTCHX->MR&0X0000003F;
 364:	b0b9      	st.w      	r5, (r0, 0x64)
{
 366:	988c      	ld.w      	r4, (sp, 0x30)
	GPTCHX->MR|=(0X01<<15)|CPC_STOP_CMD|CPC_DisCountClk_CMD|CPC_Reload_CMD|TIOA_SWTRG_OutPutX|TIOA_EEVT_OutPutX|TIOA_CPA_OutPutX|TIOA_CPC_OutPutX
 368:	6c8c      	or      	r2, r3
 36a:	90b9      	ld.w      	r5, (r0, 0x64)
{
 36c:	b880      	st.w      	r4, (sp, 0)
	GPTCHX->MR|=(0X01<<15)|CPC_STOP_CMD|CPC_DisCountClk_CMD|CPC_Reload_CMD|TIOA_SWTRG_OutPutX|TIOA_EEVT_OutPutX|TIOA_CPA_OutPutX|TIOA_CPC_OutPutX
 36e:	6c48      	or      	r1, r2
					|TIOB_SWTRG_OutPutX|TIOB_EEVT_OutPutX|TIOB_CPB_OutPutX|TIOB_CPC_OutPutX;
	if(EEVT_Reload_CMD==EEVT_Reload_ENABLE)
 370:	9860      	ld.w      	r3, (sp, 0)
	GPTCHX->MR|=(0X01<<15)|CPC_STOP_CMD|CPC_DisCountClk_CMD|CPC_Reload_CMD|TIOA_SWTRG_OutPutX|TIOA_EEVT_OutPutX|TIOA_CPA_OutPutX|TIOA_CPC_OutPutX
 372:	6d44      	or      	r5, r1
 374:	b0b9      	st.w      	r5, (r0, 0x64)
	if(EEVT_Reload_CMD==EEVT_Reload_ENABLE)
 376:	3b41      	cmpnei      	r3, 1
{
 378:	988d      	ld.w      	r4, (sp, 0x34)
	{
		GPTCHX->MR|=(0x00<<12);
 37a:	9079      	ld.w      	r3, (r0, 0x64)
	if(EEVT_Reload_CMD==EEVT_Reload_ENABLE)
 37c:	0811      	bt      	0x39e	// 39e <GPTCHX_PWM_Configure+0x84>
 37e:	0409      	br      	0x390	// 390 <GPTCHX_PWM_Configure+0x76>
	...
	}
	else
	{
		GPTCHX->MR|=(0x01<<12);
	}
	if(EEVT_SET_X==EEVT_TIOB_NONE)
 390:	3c4a      	cmpnei      	r4, 10
		GPTCHX->MR|=(0x01<<12);
 392:	b079      	st.w      	r3, (r0, 0x64)
	if(EEVT_SET_X==EEVT_TIOB_NONE)
 394:	0807      	bt      	0x3a2	// 3a2 <GPTCHX_PWM_Configure+0x88>
	{
		GPTCHX->MR|=(0x00<<10)|(0x00<<8);
 396:	9079      	ld.w      	r3, (r0, 0x64)
	{
		GPTCHX->MR|=(0x03<<10)|(0x02<<8);
	}
	else if(EEVT_SET_X==EEVT_XC2_Rise_Fall)
	{
		GPTCHX->MR|=(0x03<<10)|(0x03<<8);
 398:	b079      	st.w      	r3, (r0, 0x64)
	}
}
 39a:	1408      	addi      	sp, sp, 32
 39c:	1484      	pop      	r4-r7
		GPTCHX->MR|=(0x01<<12);
 39e:	3bac      	bseti      	r3, r3, 12
 3a0:	07f8      	br      	0x390	// 390 <GPTCHX_PWM_Configure+0x76>
	else if(EEVT_SET_X==EEVT_TIOB_Rise)
 3a2:	3c4b      	cmpnei      	r4, 11
 3a4:	0804      	bt      	0x3ac	// 3ac <GPTCHX_PWM_Configure+0x92>
		GPTCHX->MR|=(0x00<<10)|(0x01<<8);
 3a6:	9079      	ld.w      	r3, (r0, 0x64)
 3a8:	3ba8      	bseti      	r3, r3, 8
 3aa:	07f7      	br      	0x398	// 398 <GPTCHX_PWM_Configure+0x7e>
	else if(EEVT_SET_X==EEVT_TIOB_Fall)
 3ac:	3c4c      	cmpnei      	r4, 12
 3ae:	0804      	bt      	0x3b6	// 3b6 <GPTCHX_PWM_Configure+0x9c>
		GPTCHX->MR|=(0x00<<10)|(0x02<<8);
 3b0:	9079      	ld.w      	r3, (r0, 0x64)
 3b2:	3ba9      	bseti      	r3, r3, 9
 3b4:	07f2      	br      	0x398	// 398 <GPTCHX_PWM_Configure+0x7e>
	else if(EEVT_SET_X==EEVT_TIOB_Rise_Fall)
 3b6:	3c4d      	cmpnei      	r4, 13
 3b8:	0805      	bt      	0x3c2	// 3c2 <GPTCHX_PWM_Configure+0xa8>
		GPTCHX->MR|=(0x00<<10)|(0x03<<8);
 3ba:	9079      	ld.w      	r3, (r0, 0x64)
 3bc:	3ba8      	bseti      	r3, r3, 8
 3be:	3ba9      	bseti      	r3, r3, 9
 3c0:	07ec      	br      	0x398	// 398 <GPTCHX_PWM_Configure+0x7e>
	else if(EEVT_SET_X==EEVT_XC0_NONE)
 3c2:	3c4e      	cmpnei      	r4, 14
 3c4:	0804      	bt      	0x3cc	// 3cc <GPTCHX_PWM_Configure+0xb2>
		GPTCHX->MR|=(0x01<<10)|(0x00<<8);
 3c6:	9079      	ld.w      	r3, (r0, 0x64)
 3c8:	3baa      	bseti      	r3, r3, 10
 3ca:	07e7      	br      	0x398	// 398 <GPTCHX_PWM_Configure+0x7e>
	else if(EEVT_SET_X==EEVT_XC0_Rise)
 3cc:	3c4f      	cmpnei      	r4, 15
 3ce:	0805      	bt      	0x3d8	// 3d8 <GPTCHX_PWM_Configure+0xbe>
		GPTCHX->MR|=(0x01<<10)|(0x01<<8);
 3d0:	9079      	ld.w      	r3, (r0, 0x64)
 3d2:	3ba8      	bseti      	r3, r3, 8
 3d4:	3baa      	bseti      	r3, r3, 10
 3d6:	07e1      	br      	0x398	// 398 <GPTCHX_PWM_Configure+0x7e>
	else if(EEVT_SET_X==EEVT_XC0_Fall)
 3d8:	3c50      	cmpnei      	r4, 16
 3da:	0805      	bt      	0x3e4	// 3e4 <GPTCHX_PWM_Configure+0xca>
		GPTCHX->MR|=(0x01<<10)|(0x02<<8);
 3dc:	9079      	ld.w      	r3, (r0, 0x64)
 3de:	3ba9      	bseti      	r3, r3, 9
 3e0:	3baa      	bseti      	r3, r3, 10
 3e2:	07db      	br      	0x398	// 398 <GPTCHX_PWM_Configure+0x7e>
	else if(EEVT_SET_X==EEVT_XC0_Rise_Fall)
 3e4:	3c51      	cmpnei      	r4, 17
 3e6:	0806      	bt      	0x3f2	// 3f2 <GPTCHX_PWM_Configure+0xd8>
		GPTCHX->MR|=(0x01<<10)|(0x03<<8);
 3e8:	32e0      	movi      	r2, 224
 3ea:	9079      	ld.w      	r3, (r0, 0x64)
 3ec:	4243      	lsli      	r2, r2, 3
		GPTCHX->MR|=(0x03<<10)|(0x03<<8);
 3ee:	6cc8      	or      	r3, r2
 3f0:	07d4      	br      	0x398	// 398 <GPTCHX_PWM_Configure+0x7e>
	else if(EEVT_SET_X==EEVT_XC1_NONE)
 3f2:	3c52      	cmpnei      	r4, 18
 3f4:	0804      	bt      	0x3fc	// 3fc <GPTCHX_PWM_Configure+0xe2>
		GPTCHX->MR|=(0x02<<10)|(0x00<<8);
 3f6:	9079      	ld.w      	r3, (r0, 0x64)
 3f8:	3bab      	bseti      	r3, r3, 11
 3fa:	07cf      	br      	0x398	// 398 <GPTCHX_PWM_Configure+0x7e>
	else if(EEVT_SET_X==EEVT_XC1_Rise)
 3fc:	3c53      	cmpnei      	r4, 19
 3fe:	0805      	bt      	0x408	// 408 <GPTCHX_PWM_Configure+0xee>
		GPTCHX->MR|=(0x02<<10)|(0x01<<8);
 400:	9079      	ld.w      	r3, (r0, 0x64)
 402:	3ba8      	bseti      	r3, r3, 8
 404:	3bab      	bseti      	r3, r3, 11
 406:	07c9      	br      	0x398	// 398 <GPTCHX_PWM_Configure+0x7e>
	else if(EEVT_SET_X==EEVT_XC1_Fall)
 408:	3c54      	cmpnei      	r4, 20
 40a:	0805      	bt      	0x414	// 414 <GPTCHX_PWM_Configure+0xfa>
		GPTCHX->MR|=(0x02<<10)|(0x02<<8);
 40c:	9079      	ld.w      	r3, (r0, 0x64)
 40e:	3ba9      	bseti      	r3, r3, 9
 410:	3bab      	bseti      	r3, r3, 11
 412:	07c3      	br      	0x398	// 398 <GPTCHX_PWM_Configure+0x7e>
	else if(EEVT_SET_X==EEVT_XC1_Rise_Fall)
 414:	3c55      	cmpnei      	r4, 21
 416:	0805      	bt      	0x420	// 420 <GPTCHX_PWM_Configure+0x106>
		GPTCHX->MR|=(0x02<<10)|(0x03<<8);
 418:	9079      	ld.w      	r3, (r0, 0x64)
 41a:	32b0      	movi      	r2, 176
		GPTCHX->MR|=(0x03<<10)|(0x03<<8);
 41c:	4244      	lsli      	r2, r2, 4
 41e:	07e8      	br      	0x3ee	// 3ee <GPTCHX_PWM_Configure+0xd4>
	else if(EEVT_SET_X==EEVT_XC2_NONE)
 420:	3c56      	cmpnei      	r4, 22
 422:	0805      	bt      	0x42c	// 42c <GPTCHX_PWM_Configure+0x112>
		GPTCHX->MR|=(0x03<<10)|(0x00<<8);
 424:	9079      	ld.w      	r3, (r0, 0x64)
 426:	3baa      	bseti      	r3, r3, 10
 428:	3bab      	bseti      	r3, r3, 11
 42a:	07b7      	br      	0x398	// 398 <GPTCHX_PWM_Configure+0x7e>
	else if(EEVT_SET_X==EEVT_XC2_Rise)
 42c:	3c57      	cmpnei      	r4, 23
 42e:	0804      	bt      	0x436	// 436 <GPTCHX_PWM_Configure+0x11c>
		GPTCHX->MR|=(0x03<<10)|(0x01<<8);
 430:	9079      	ld.w      	r3, (r0, 0x64)
 432:	32d0      	movi      	r2, 208
 434:	07f4      	br      	0x41c	// 41c <GPTCHX_PWM_Configure+0x102>
	else if(EEVT_SET_X==EEVT_XC2_Fall)
 436:	3c58      	cmpnei      	r4, 24
 438:	0804      	bt      	0x440	// 440 <GPTCHX_PWM_Configure+0x126>
		GPTCHX->MR|=(0x03<<10)|(0x02<<8);
 43a:	9079      	ld.w      	r3, (r0, 0x64)
 43c:	32e0      	movi      	r2, 224
 43e:	07ef      	br      	0x41c	// 41c <GPTCHX_PWM_Configure+0x102>
	else if(EEVT_SET_X==EEVT_XC2_Rise_Fall)
 440:	3c59      	cmpnei      	r4, 25
 442:	0bac      	bt      	0x39a	// 39a <GPTCHX_PWM_Configure+0x80>
		GPTCHX->MR|=(0x03<<10)|(0x03<<8);
 444:	9079      	ld.w      	r3, (r0, 0x64)
 446:	32f0      	movi      	r2, 240
 448:	07ea      	br      	0x41c	// 41c <GPTCHX_PWM_Configure+0x102>

0000044a <GPTCHX_Capture_Configure>:
//LDRB_TIOA_SET_X:LDRB_TIOA_NONE,LDRB_TIOA_Rise,LDRB_TIOA_Fall,LDRB_TIOA_Rise_Fall
//ReturnValue:NONE
/*************************************************************/ 
void GPTCHX_Capture_Configure(CSP_GPT_T *GPTCHX , LDB_STOP_CMD_TypeDef LDB_STOP_CMD_X , LDB_DISCountClk_CMD_TypeDef LDB_DIS_CMD_X , 
		ABETRG_SET_TypeDef ABETRG_SET_X , CPC_TRG_CMD_TypeDef CPC_Reload_CMD , LDRA_TIOA_SET_TypeDef LDRA_TIOA_SET_X , LDRB_TIOA_SET_TypeDef LDRB_TIOA_SET_X)
{
 44a:	14c4      	push      	r4-r7
 44c:	1421      	subi      	sp, sp, 4
 44e:	9885      	ld.w      	r4, (sp, 0x14)
 450:	6dd3      	mov      	r7, r4
 452:	9886      	ld.w      	r4, (sp, 0x18)
 454:	6d93      	mov      	r6, r4
 456:	9887      	ld.w      	r4, (sp, 0x1c)
 458:	b880      	st.w      	r4, (sp, 0)
	GPTCHX->MR=GPTCHX->MR&0X0000003F;
 45a:	353f      	movi      	r5, 63
 45c:	9099      	ld.w      	r4, (r0, 0x64)
 45e:	6914      	and      	r4, r5
	GPTCHX->MR|=CPC_Reload_CMD|LDB_STOP_CMD_X|LDB_DIS_CMD_X|LDRA_TIOA_SET_X|LDRB_TIOA_SET_X;
 460:	6d5b      	mov      	r5, r6
 462:	98c0      	ld.w      	r6, (sp, 0)
 464:	6d58      	or      	r5, r6
 466:	6c94      	or      	r2, r5
	GPTCHX->MR=GPTCHX->MR&0X0000003F;
 468:	b099      	st.w      	r4, (r0, 0x64)
	GPTCHX->MR|=CPC_Reload_CMD|LDB_STOP_CMD_X|LDB_DIS_CMD_X|LDRA_TIOA_SET_X|LDRB_TIOA_SET_X;
 46a:	6c48      	or      	r1, r2
 46c:	9099      	ld.w      	r4, (r0, 0x64)
 46e:	6c5c      	or      	r1, r7
 470:	6c50      	or      	r1, r4
	if(ABETRG_SET_X==ABETRG_TIOA_NONE)
 472:	3b4a      	cmpnei      	r3, 10
	GPTCHX->MR|=CPC_Reload_CMD|LDB_STOP_CMD_X|LDB_DIS_CMD_X|LDRA_TIOA_SET_X|LDRB_TIOA_SET_X;
 474:	b039      	st.w      	r1, (r0, 0x64)
	if(ABETRG_SET_X==ABETRG_TIOA_NONE)
 476:	0806      	bt      	0x482	// 482 <GPTCHX_Capture_Configure+0x38>
	{
		GPTCHX->MR|=(0x01<<10)|(0x00<<8);
 478:	9079      	ld.w      	r3, (r0, 0x64)
 47a:	3baa      	bseti      	r3, r3, 10
	{
		GPTCHX->MR|=(0x00<<10)|(0x02<<8);
	}
	else if(ABETRG_SET_X==ABETRG_TIOB_Rise_Fall)
	{
		GPTCHX->MR|=(0x00<<10)|(0x03<<8);
 47c:	b079      	st.w      	r3, (r0, 0x64)
	}
}
 47e:	1401      	addi      	sp, sp, 4
 480:	1484      	pop      	r4-r7
	else if(ABETRG_SET_X==ABETRG_TIOA_Rise)
 482:	3b4b      	cmpnei      	r3, 11
 484:	0805      	bt      	0x48e	// 48e <GPTCHX_Capture_Configure+0x44>
		GPTCHX->MR|=(0x01<<10)|(0x01<<8);
 486:	9079      	ld.w      	r3, (r0, 0x64)
 488:	3ba8      	bseti      	r3, r3, 8
 48a:	3baa      	bseti      	r3, r3, 10
 48c:	07f8      	br      	0x47c	// 47c <GPTCHX_Capture_Configure+0x32>
	else if(ABETRG_SET_X==ABETRG_TIOA_Fall)
 48e:	3b4c      	cmpnei      	r3, 12
 490:	0805      	bt      	0x49a	// 49a <GPTCHX_Capture_Configure+0x50>
		GPTCHX->MR|=(0x01<<10)|(0x02<<8);
 492:	9079      	ld.w      	r3, (r0, 0x64)
 494:	3ba9      	bseti      	r3, r3, 9
 496:	3baa      	bseti      	r3, r3, 10
 498:	07f2      	br      	0x47c	// 47c <GPTCHX_Capture_Configure+0x32>
	else if(ABETRG_SET_X==ABETRG_TIOA_Rise_Fall)
 49a:	3b4d      	cmpnei      	r3, 13
 49c:	0806      	bt      	0x4a8	// 4a8 <GPTCHX_Capture_Configure+0x5e>
		GPTCHX->MR|=(0x01<<10)|(0x03<<8);
 49e:	32e0      	movi      	r2, 224
 4a0:	9079      	ld.w      	r3, (r0, 0x64)
 4a2:	4243      	lsli      	r2, r2, 3
 4a4:	6cc8      	or      	r3, r2
 4a6:	07eb      	br      	0x47c	// 47c <GPTCHX_Capture_Configure+0x32>
	else if(ABETRG_SET_X==ABETRG_TIOB_NONE)
 4a8:	3b4e      	cmpnei      	r3, 14
 4aa:	0803      	bt      	0x4b0	// 4b0 <GPTCHX_Capture_Configure+0x66>
		GPTCHX->MR|=(0x00<<10)|(0x00<<8);
 4ac:	9079      	ld.w      	r3, (r0, 0x64)
 4ae:	07e7      	br      	0x47c	// 47c <GPTCHX_Capture_Configure+0x32>
	else if(ABETRG_SET_X==ABETRG_TIOB_Rise)
 4b0:	3b4f      	cmpnei      	r3, 15
 4b2:	0804      	bt      	0x4ba	// 4ba <GPTCHX_Capture_Configure+0x70>
		GPTCHX->MR|=(0x00<<10)|(0x01<<8);
 4b4:	9079      	ld.w      	r3, (r0, 0x64)
 4b6:	3ba8      	bseti      	r3, r3, 8
 4b8:	07e2      	br      	0x47c	// 47c <GPTCHX_Capture_Configure+0x32>
	else if(ABETRG_SET_X==ABETRG_TIOB_Fall)
 4ba:	3b50      	cmpnei      	r3, 16
 4bc:	0804      	bt      	0x4c4	// 4c4 <GPTCHX_Capture_Configure+0x7a>
		GPTCHX->MR|=(0x00<<10)|(0x02<<8);
 4be:	9079      	ld.w      	r3, (r0, 0x64)
 4c0:	3ba9      	bseti      	r3, r3, 9
 4c2:	07dd      	br      	0x47c	// 47c <GPTCHX_Capture_Configure+0x32>
	else if(ABETRG_SET_X==ABETRG_TIOB_Rise_Fall)
 4c4:	3b51      	cmpnei      	r3, 17
 4c6:	0bdc      	bt      	0x47e	// 47e <GPTCHX_Capture_Configure+0x34>
		GPTCHX->MR|=(0x00<<10)|(0x03<<8);
 4c8:	9079      	ld.w      	r3, (r0, 0x64)
 4ca:	3ba8      	bseti      	r3, r3, 8
 4cc:	3ba9      	bseti      	r3, r3, 9
 4ce:	07d7      	br      	0x47c	// 47c <GPTCHX_Capture_Configure+0x32>

000004d0 <GPTCHX_ConfigInterrupt_CMD>:
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/ 
void GPTCHX_ConfigInterrupt_CMD(CSP_GPT_T *GPTCHX , GPTCHX_INT_TypeDef GPTCHX_INT_X , FunctionalStatus NewState)
{
	if (NewState != DISABLE)
 4d0:	3a40      	cmpnei      	r2, 0
 4d2:	0c07      	bf      	0x4e0	// 4e0 <GPTCHX_ConfigInterrupt_CMD+0x10>
	{
		GPTCHX->IER  = GPTCHX_INT_X;					//SET
 4d4:	b03d      	st.w      	r1, (r0, 0x74)
		while(!(GPTCHX->IMR&GPTCHX_INT_X));
 4d6:	907f      	ld.w      	r3, (r0, 0x7c)
 4d8:	68c4      	and      	r3, r1
 4da:	3b40      	cmpnei      	r3, 0
 4dc:	0ffd      	bf      	0x4d6	// 4d6 <GPTCHX_ConfigInterrupt_CMD+0x6>
	else
	{
		GPTCHX->IDR  =	GPTCHX_INT_X;					//CLR
		while(GPTCHX->IMR&GPTCHX_INT_X);
	}
}
 4de:	783c      	rts
		GPTCHX->IDR  =	GPTCHX_INT_X;					//CLR
 4e0:	b03e      	st.w      	r1, (r0, 0x78)
		while(GPTCHX->IMR&GPTCHX_INT_X);
 4e2:	907f      	ld.w      	r3, (r0, 0x7c)
 4e4:	68c4      	and      	r3, r1
 4e6:	3b40      	cmpnei      	r3, 0
 4e8:	0bfd      	bt      	0x4e2	// 4e2 <GPTCHX_ConfigInterrupt_CMD+0x12>
 4ea:	07fa      	br      	0x4de	// 4de <GPTCHX_ConfigInterrupt_CMD+0xe>

000004ec <GPTCH0_Int_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPTCH0_Int_Enable(void)
{
    INTC_ISER_WRITE(TC0_0_INT);    
 4ec:	116a      	lrw      	r3, 0	// 594 <GPTCH2_Wakeup_Disable+0x10>
 4ee:	3210      	movi      	r2, 16
 4f0:	9360      	ld.w      	r3, (r3, 0)
 4f2:	23ff      	addi      	r3, 256
 4f4:	b340      	st.w      	r2, (r3, 0)
}
 4f6:	783c      	rts

000004f8 <GPTCH1_Int_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPTCH1_Int_Enable(void)
{
    INTC_ISER_WRITE(TC0_1_INT);    
 4f8:	1167      	lrw      	r3, 0	// 594 <GPTCH2_Wakeup_Disable+0x10>
 4fa:	3220      	movi      	r2, 32
 4fc:	9360      	ld.w      	r3, (r3, 0)
 4fe:	23ff      	addi      	r3, 256
 500:	b340      	st.w      	r2, (r3, 0)
}
 502:	783c      	rts

00000504 <GPTCH2_Int_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPTCH2_Int_Enable(void)
{
    INTC_ISER_WRITE(TC0_2_INT);    
 504:	1164      	lrw      	r3, 0	// 594 <GPTCH2_Wakeup_Disable+0x10>
 506:	3240      	movi      	r2, 64
 508:	9360      	ld.w      	r3, (r3, 0)
 50a:	23ff      	addi      	r3, 256
 50c:	b340      	st.w      	r2, (r3, 0)
}
 50e:	783c      	rts

00000510 <GPTCH0_Int_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPTCH0_Int_Disable(void)
{
    INTC_ICER_WRITE(TC0_0_INT);    
 510:	1161      	lrw      	r3, 0	// 594 <GPTCH2_Wakeup_Disable+0x10>
 512:	32c0      	movi      	r2, 192
 514:	9360      	ld.w      	r3, (r3, 0)
 516:	4241      	lsli      	r2, r2, 1
 518:	60c8      	addu      	r3, r2
 51a:	3210      	movi      	r2, 16
 51c:	b340      	st.w      	r2, (r3, 0)
}
 51e:	783c      	rts

00000520 <GPTCH1_Int_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPTCH1_Int_Disable(void)
{
    INTC_ICER_WRITE(TC0_1_INT);    
 520:	107d      	lrw      	r3, 0	// 594 <GPTCH2_Wakeup_Disable+0x10>
 522:	32c0      	movi      	r2, 192
 524:	9360      	ld.w      	r3, (r3, 0)
 526:	4241      	lsli      	r2, r2, 1
 528:	60c8      	addu      	r3, r2
 52a:	3220      	movi      	r2, 32
 52c:	b340      	st.w      	r2, (r3, 0)
}
 52e:	783c      	rts

00000530 <GPTCH2_Int_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPTCH2_Int_Disable(void)
{
    INTC_ICER_WRITE(TC0_2_INT);    
 530:	1079      	lrw      	r3, 0	// 594 <GPTCH2_Wakeup_Disable+0x10>
 532:	32c0      	movi      	r2, 192
 534:	9360      	ld.w      	r3, (r3, 0)
 536:	4241      	lsli      	r2, r2, 1
 538:	60c8      	addu      	r3, r2
 53a:	3240      	movi      	r2, 64
 53c:	b340      	st.w      	r2, (r3, 0)
}
 53e:	783c      	rts

00000540 <GPTCH0_Wakeup_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPTCH0_Wakeup_Enable(void)
{
    INTC_IWER_WRITE(TC0_0_INT);    
 540:	1075      	lrw      	r3, 0	// 594 <GPTCH2_Wakeup_Disable+0x10>
 542:	3210      	movi      	r2, 16
 544:	9360      	ld.w      	r3, (r3, 0)
 546:	23ff      	addi      	r3, 256
 548:	b350      	st.w      	r2, (r3, 0x40)
}
 54a:	783c      	rts

0000054c <GPTCH0_Wakeup_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPTCH0_Wakeup_Disable(void)
{
    INTC_IWDR_WRITE(TC0_0_INT);    
 54c:	1072      	lrw      	r3, 0	// 594 <GPTCH2_Wakeup_Disable+0x10>
 54e:	32e0      	movi      	r2, 224
 550:	9360      	ld.w      	r3, (r3, 0)
 552:	4241      	lsli      	r2, r2, 1
 554:	60c8      	addu      	r3, r2
 556:	3210      	movi      	r2, 16
 558:	b340      	st.w      	r2, (r3, 0)
}
 55a:	783c      	rts

0000055c <GPTCH1_Wakeup_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPTCH1_Wakeup_Enable(void)
{
    INTC_IWER_WRITE(TC0_1_INT);    
 55c:	106e      	lrw      	r3, 0	// 594 <GPTCH2_Wakeup_Disable+0x10>
 55e:	3220      	movi      	r2, 32
 560:	9360      	ld.w      	r3, (r3, 0)
 562:	23ff      	addi      	r3, 256
 564:	b350      	st.w      	r2, (r3, 0x40)
}
 566:	783c      	rts

00000568 <GPTCH1_Wakeup_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPTCH1_Wakeup_Disable(void)
{
    INTC_IWDR_WRITE(TC0_1_INT);    
 568:	106b      	lrw      	r3, 0	// 594 <GPTCH2_Wakeup_Disable+0x10>
 56a:	32e0      	movi      	r2, 224
 56c:	9360      	ld.w      	r3, (r3, 0)
 56e:	4241      	lsli      	r2, r2, 1
 570:	60c8      	addu      	r3, r2
 572:	3220      	movi      	r2, 32
 574:	b340      	st.w      	r2, (r3, 0)
}
 576:	783c      	rts

00000578 <GPTCH2_Wakeup_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPTCH2_Wakeup_Enable(void)
{
    INTC_IWER_WRITE(TC0_2_INT);    
 578:	1067      	lrw      	r3, 0	// 594 <GPTCH2_Wakeup_Disable+0x10>
 57a:	3240      	movi      	r2, 64
 57c:	9360      	ld.w      	r3, (r3, 0)
 57e:	23ff      	addi      	r3, 256
 580:	b350      	st.w      	r2, (r3, 0x40)
}
 582:	783c      	rts

00000584 <GPTCH2_Wakeup_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GPTCH2_Wakeup_Disable(void)
{
    INTC_IWDR_WRITE(TC0_2_INT);    
 584:	1064      	lrw      	r3, 0	// 594 <GPTCH2_Wakeup_Disable+0x10>
 586:	32e0      	movi      	r2, 224
 588:	9360      	ld.w      	r3, (r3, 0)
 58a:	4241      	lsli      	r2, r2, 1
 58c:	60c8      	addu      	r3, r2
 58e:	3240      	movi      	r2, 64
 590:	b340      	st.w      	r2, (r3, 0)
}
 592:	783c      	rts
 594:	00000000 	.long	0x00000000
